Simulation of Field-Plate Effects on Lag and Current Collapse in GaN-based FETs

	Nanotech 2008 Vol. 3 Nanotechnology 2008: Microsystems, Photonics, Sensors, Fluidics, Modeling, and Simulation - Technical Proceedings of the 2008 NSTI Nanotechnology Conference and Trade Show, Volume 3 Chapter 5: Modeling & Simulation of Microsystems
	Simulation of Field-Plate Effects on Lag and Current Collapse in GaN-based FETs
Authors:	K. Itagaki, A. Nakajima, K. Horio
Affilation:	Shibaura Institute of Technology, JP
Pages:	533 - 536
Keywords:	GaN, FET, field plate, current collapse, trap
Abstract:	Two-dimensional transient analyses of field-plate GaN MESFETs and AlGaN/GaN HEMTs with a semi-insulating buffer layer have been performed in which a deep donor and a deep acceptor are considered in the buffer layer. Quasi-pulsed I-V curves are derived from the transient characteristics. It is shown that drain lag is reduced by introducing a field plate because trapping effects become smaller. It is also shown that the current collapse and gate lag are also reduced in the field-plate structure. It is suggested that there is an optimum thickness of SiN passivation layer to minimize the buffer-related current collapse and drain lag in GaN-based FETs.
ISBN:	978-1-4200-8505-1
Pages:	940
Hardcopy:	$159.95

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