Nanotech 2008 Vol. 3
Nanotech 2008 Vol. 3
Nanotechnology 2008: Microsystems, Photonics, Sensors, Fluidics, Modeling, and Simulation - Technical Proceedings of the 2008 NSTI Nanotechnology Conference and Trade Show, Volume 3

Modeling & Simulation of Microsystems Chapter 5

Pre-Distortion Assessment of Workfunction Engineered Multilayer Dielectric Design of DMG ISE SON MOSFET

Authors: R. Kaur, R. Chaujar, M. Saxena, R.S. Gupta

Affilation: Semiconductor Devices Research Laboratory, India

Pages: 605 - 606

Keywords: DM, ISE, SON, intermodulation

Abstract:
To overcome miniaturization roadblock, innovative architectural enhancements involving the use of an improved SOI like architecture called Silicon On Nothing (SON) capable of SCE and DIBL suppression onto the existing ISE devices [2], has been considered for SCEs suppression. Further to overcome the electron transport inefficiency, Dual Material Gate (DMG) architecture has also been integrated thereby presenting ultimate device architecture of DMG ISE SON MOSFET for ULSI era. In this work, linearity performance of 50nm DMG ISE SON MOSFET has been investigated and compared with other Single/ Dual Material Gate (S/DMG) taking into consideration the non-equilibrium transport effect implemented via Energy Balance Transport (EBT) model activated through ATLAS-2D device simulation software. The work discusses the linearity Figure of Merits -VIP2, VIP3 and third order intermodulation distortion IMD3 and thereby, provides optimal bias point selection

Pre-Distortion Assessment of Workfunction Engineered Multilayer Dielectric Design of DMG ISE SON MOSFET

ISBN: 978-1-4200-8505-1
Pages: 940
Hardcopy: $159.95