Authors: M.J. Kumar, S. Saurabh
Affilation: Indian Institute of Technology, India
Pages: 28 - 30
Keywords: tunneling, strained-silicon, SOI MOSFET, short-channel effects, TFET, two-dimensional simulation
Quantum tunneling devices are very promising as they have very low leakage current and show good scalability. However, the most serious drawback for tunneling devices hampering their wide-scale CMOS application is their low on-current and high threshold voltage. In this paper, we propose a novel lateral Strained Double-Gate Tunnel Field Effect Transistor (SDGTFET), which not only tackles these problems very well but also shows excellent overall device characteristics. For the first time, using two dimensional simulation, we show that the proposed device improves the on-current by two-order of magnitude without significantly degrading the off-current, lowers the threshold voltage so as to meet the ITRS guideline, improves the average subthreshold swing and also shows good immunity to short channel effects.