3D Nanostructured Silicon Relying on Hard Mask Engineering for High Temperature Annealing (HME-HTA) Processes for Electronic Devices

	Nanotech 2008 Vol. 1 Nanotechnology 2008: Materials, Fabrication, Particles, and Characterization - Technical Proceedings of the 2008 NSTI Nanotechnology Conference and Trade Show, Volume 1 Chapter 4: Nanofabrication & Direct-Write Nanolithography
	3D Nanostructured Silicon Relying on Hard Mask Engineering for High Temperature Annealing (HME-HTA) Processes for Electronic Devices
Authors:	M. Bopp, P. Coronel, F. Judong, K. Jouannic, A. Talbot, D. Ristoiu, C. Pribat, N. Bardos, F. Pico, M.P. Samson, P. Dainesi, A.M. Ionescu, T. Skotnicki
Affilation:	Ecole Polytechnique Fédérale de Lausanne, CH
Pages:	634 - 637
Keywords:	silicon high temperature annealing, hard mask, buried cavity, Independant double gate transistor
Abstract:	Annealing silicon at high temperatures in hydrogen ambiance has been reported to induce surface diffusion of silicon; in these conditions, adapted 2D arrays of trenches etched in Bulk Si are transformed into buried cavities creating suspended membranes. A 3D nanostructuration of silicon through hard mask engineering and high temperature annealing in hydrogen ambiance is reported. By using a nitride-oxide hard mask stack instead of a sacrificial oxide hard mask for a free surface (maskless) annealing, we open new technological and design possibilities using 2D arrays of various geometry trenches. Implications and potential device applications are discussed.
ISBN:	978-1-4200-8503-7
Pages:	1,118
Hardcopy:	$159.95

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