Nano Science and Technology Institute
Nanotech 2008 Vol. 1
Nanotech 2008 Vol. 1
Nanotechnology 2008: Materials, Fabrication, Particles, and Characterization - Technical Proceedings of the 2008 NSTI Nanotechnology Conference and Trade Show, Volume 1
 
Chapter 2: Nano Materials & Composites
 

An FPGA Architecture Using Vertical Silicon Nanowire Transistors

Authors:A. Bindal, D. Wickramaratne, S. Hamedi-Hagh
Affilation:San Jose State University, US
Pages:250 - 253
Keywords:nanowire transistors, nano-architecture, FPGA
Abstract:This study presents an FPGA architecture using vertical silicon nanowire transistors. A complete picture from designing ultra low-power silicon nanowire transistors to their use in an FPGA architecture is given. Post-layout, worst-case rise delay changes with TR = 9FO + 61 in ps where FO corresponds to cluster fan-out; the fall delay similarly changes with TF = 12.5FO + 59.5 in ps. Average dynamic power dissipation measured at 10GHz is 3.1µW for a 4-LUT and 10.2µW for a cluster. A single 4-LUT occupies in the neighborhood of 2.6µm2 layout area. The total layout area of an FPGA cluster measures approximately 8.0µm2.
An FPGA Architecture Using Vertical Silicon Nanowire TransistorsView PDF of paper
ISBN:978-1-4200-8503-7
Pages:1,118
Hardcopy:$159.95
 
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