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 | Nanotech 2007 Vol. 3
Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 7: Compact Modeling |
| | High Voltage MOSFET’s Modeling Review | | Authors: | Y. Ma, M-C Jeng and Z. Liu | | Affilation: | Cadence Design System, Inc., US | | Pages: | 586 - 589 | | Keywords: | LDMOS, HVMOS, macro model, compact model | | Abstract: | In this paper, different modeling solutions for HVMOS and LDMOS are discussed, current status of compact model development for HVMOS/LDMOS are reviewed. Macro models are widely used to model HVMOS and LDMOS devices. Different macro models used in HVMOS/LDMOS modeling are presented including bias dependent resistance approach, JFET approach and verilogA approach. Macro models have the advantages of simulator independency and flexibility to fit different device structures. However, it often suffers from performance and convergence issues. Compared with macro model approach, compact model has obvious advantages. It can accurately model DC, AC and high frequency behavior of the high voltage devices. It can easily model self-heating effect. And compact model approach usually has better performance and convergence behavior. History and current status of HVMOS/LDMOS compact models are reviewed. Early stage of compact model development for HVMOS devices, represented by Cadence HVMOS model, was empirical. The quasi-saturation behavior in HVMOS devices is modeled by changing saturation velocity formulation to include gate bias dependency. Newly developed physics-based LDMOS models usually use bias dependent drift region resistance to model the quasi-saturation behavior. Several unique features of LDMOS/HVMOS devices and their modeling approaches are discussed. Those includes quasi-saturation, bias dependency of drift region resistance, non-uniform doping in channel region, substrate current, self-heating effect, distributed RC network effect on charge model. | | ISBN: | 1-4200-6184-4 |
| Pages: | 732 |
| Hardcopy: | $199.99 |
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