Nanotech 2007 Vol. 3
Nanotech 2007 Vol. 3
Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 3

Compact Modeling Chapter 7

Carbon Nanotube Transistor Compact Model

Authors: J. Deng, G.C. Wan and H.-S. Wong

Affilation: Stanford University, United States

Pages: 544 - 547

Keywords: carbon nanotube transistor, SPICE model, compact model

The principal challenges for the semiconductor industry at the nanoscale are: (1) power and performance optimization, (2) device fabrication and control of variations at the nanoscale, and (3) integration of a diverse set of materials and devices on the same chip. , Nanotechnology has been put forward as the key to meeting many of the challenges of the industry. New physical phenomenon and chemical/biological synthesis techniques are being explored. While there have been significant accomplishments in scientific discovery at the nanoscale, the engineering work that is required to harness the science into manufacturable technologies is just beginning. In this paper, we focus on the use of the carbon nanotube transistor as a logic switch. While very promising experimental results have been published in the past few years, these results are mostly on a single-device level with a focus on scientific discovery. In order to develop a new transistor into a bona fide technology, an engineering approach needs to be adopted. We need to develop the necessary device models and design tools with the appropriate level of abstraction to enable the design of a useful system. This is distinct from the “science” phase of discovery and explanation of physical phenomena. We will describe the development of an HSPICE compact model of the carbon nanotube transistor . The model is physics based and include non-idealities such as carrier scattering and parasitic resistances and parasitic capacitances. Using this model, we perform circuit simulations to assess the effect of material parameter variation of the carbon nanotube on circuit performance. We obtain key information such as the delay variation as a function of the nanotube diameter and the source/drain doping level and thereby establish a realistic assessment of the expected performance of carbon nanotube transistors at the circuit level. This device model is compatible with both digital circuits design (as a logic switch) and analog circuits design (as small signal amplifier). We illustrate the use of this model for small signal analysis through an application example . The development of tools, such as the ones illustrated in this paper, will be necessary for any proposed new device to become a useful technology.

Carbon Nanotube Transistor Compact Model

ISBN: 1-4200-6184-4
Pages: 732
Hardcopy: $139.95