Nano Science and Technology Institute
Nanotech 2007 Vol. 3
Nanotech 2007 Vol. 3
Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 3
 
Chapter 3: Sensors & MEMS
 

Silex offers sub 50 um pitch for through wafer connections in up to 600 um thick substrates

Authors:T. Bauer
Affilation:Silex Microsystems, SE
Pages:116 - 119
Keywords:through silicon via, 3d interconnect, wafer level packaging, low pitch via, high density via, interposer, CSP, chip scale packaging
Abstract:The silicon via process developed by Silex offers sub 50 um via pitch for through wafer connections in up to 600 um thick wafers. Silex via process enables MEMS designs with significantly reduced die size and true "Wafer Level Packaging" - features that are particularly important in consumer market applications. The through wafer interconnect technology also enables integration of advanced interconnect functions in optical MEMS, sensors and microfluidic devices. With more than 10 foundry customers using the process today and an extraordinary line-up of potential users, Silex aims at making the process a standard in the MEMS industry. The swift propagation of the technology will be facilitated by reasonable licensing fees as well as technology transfer programs with customers who favor incorporating the technology in their existing manufacturing lines.
Silex offers sub 50 um pitch for through wafer connections in up to 600 um thick substratesView PDF of paper
ISBN:1-4200-6184-4
Pages:732
Hardcopy:$139.95
 
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