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 | Nanotech 2007 Vol. 3
Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 2: MEMS/NEMS: Modeling & Characterization |
| | A Study on the Electrical Properties of Plasma Nitrided Oxide Gate Dielectric in Flash Memory | | Authors: | M. Park, K. Suh, S. Lee, H. Kang, K. Kim and K. Kim | | Affilation: | Samsung Electronics, KR | | Pages: | 85 - 88 | | Keywords: | plasma nitridation, device simulation, trap | | Abstract: | In this paper, we address the effect of Plasma Nitridation on the gate dielectric by a combined experimental and simulation study of gate oxidation. Firstly, Boron segregation at the Si/SiO2 interface is experimentally characterized by means of 1D SIMS, confirming that plasma nitrided gate dielectric possesses the same boron concentration profile on Si as the gate dielectric with dry oxidation. Secondly, a comprehensive process simulation model is accurately calibrated and then exploited to investigate the dependence of device electrical parameters on NMOS/PMOS Transistors. In experiment, VTH of NMOS and PMOS transistor of nitrided gate oxide shows 0.1V lower value than that of dry oxidation. In the device simulation, we identify that the positive trap generated by Plasma Nitridation causes the VTH shift, and it is confirmed by reproducing the unusual shape of buried channel PMOS C-V diagram of the plasma nitrided gate dielectric. | | ISBN: | 1-4200-6184-4 |
| Pages: | 732 |
| Hardcopy: | $199.99 |
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