Nanotech 2007 Vol. 1
Nanotech 2007 Vol. 1
Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 1

Nanoscale Modeling Chapter 6

The Innitial Reverse-Bias Injecting P+-N Junction Mode in P+-N-P+- Structures with Punch-Through

Authors: I. Mats

Affilation: Diatex, Selected Texno-Fix, Canada

Pages: 485 - 488

Keywords: bipolar transistors, current leakage, design, FETs, punchthrough, shape, space charge, space charge limited conduction

Abstract:
The Volt-Ampere Characteristics (VAC)s of P+NP+-structures in the schemes with floating base and short-cut p+-n junction (emitter) in punch-through modes were calculated before. It is important to research a behavior for similar structures but with initial reverse-bias (Uer) injecting p+-n -junction. Calculation and experimental characteristics VACs for lateral and vertical devices has good consultation. P+NP+ (N+PN+) – Devices in this mode can be used in variety Field-Effect Transistors including four terminals, DEPFETs, Punchthrough FETs, Bipolar transistors, Protection elements, Electrostatic dischargers, Charge coupled and photo punch-through devices, Reference sources, and Amplifiers.

The Innitial Reverse-Bias Injecting P+-N Junction Mode in P+-N-P+- Structures with Punch-Through

ISBN: 1-4200-6182-8
Pages: 726
Hardcopy: $139.95