Authors: E. Seebacher, W. Posch, K. Molnar and Z. Huszka
Affilation: austriamicrosystems AG, Austria
Pages: 720 - 723
Keywords: HV MOS transistor, compact modeling, mismatch, SPICE sub-circuit
In this paper we discuss state of the art and new developments of analog modeling for HV CMOS technologies. We will give a detailed overview about the full characterization of a 0.35um high voltage process for analog/HV application. We describe the SPICE modeling of a HV MOS transistor with a sub-circuit including quasi-saturation effect, geometry scaling, lateral doping and parasitic substrate current effects. Additionally a proper mismatch model for HV CMOS transistors including an efficient parameter extraction strategy will be shown.