Authors: A. Botula, S. Furkay, D.C. Sheridan, J.M. Johnson and M-H Na
Affilation: IBM Corporation, United States
Pages: 828 - 830
Keywords: TCAD SOI compact model
This work describes a TCAD-based methodology for generating compact models for circuit design in advance of hardware availability (predictive modeling). The exercise was performed on a 65nm node SOI CMOS technology. TCAD simulations accurate enough for predicting quantitative results require a novel calibration methodology to hardware over broad geometry, bias, and temperature ranges. NFET and PFET compact models were extracted from TCAD-generated<br>I-V data and the quality of model fit was shown to be very good.