Nano Science and Technology Institute
Nanotech 2006 Vol. 3
Nanotech 2006 Vol. 3
Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3
 
Chapter 7: Compact Modeling
 

SOI CMOS Compact Modeling based on TCAD Device Simulations

Authors:A. Botula, S. Furkay, D.C. Sheridan, J.M. Johnson and M-H Na
Affilation:IBM Corporation, US
Pages:828 - 830
Keywords:TCAD SOI compact model
Abstract:This work describes a TCAD-based methodology for generating compact models for circuit design in advance of hardware availability (predictive modeling). The exercise was performed on a 65nm node SOI CMOS technology. TCAD simulations accurate enough for predicting quantitative results require a novel calibration methodology to hardware over broad geometry, bias, and temperature ranges. NFET and PFET compact models were extracted from TCAD-generated
I-V data and the quality of model fit was shown to be very good.
SOI CMOS Compact Modeling based on TCAD Device SimulationsView PDF of paper
ISBN:0-9767985-8-1
Pages:913
Hardcopy:$119.95
 
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