Nano Science and Technology Institute
Nanotech 2006 Vol. 3
Nanotech 2006 Vol. 3
Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 7: Compact Modeling

Capacitance Model for Four-Terminal DG MOSFETs

Authors:T. Nakagawa, T. Sekigawa, T. Tsutsumi, M. Hioki, S. O’uchi and H. Koike
Affilation:National Institute of Advanced Industrial Science and Technology, JP
Pages:800 - 803
Keywords:double-gate, compact model, capacitance model
Abstract:We present an intrinsic-capacitance model for undoped-channel full-deplete DG MOSFETs with two independent gates of different gate-oxide thickness. It includes carrier-velocity saturation, and mobility change by the surface electric-field. We considered five intrinsic capacitances Cg1s, Cg1d, Cg2s, Cg2d, and Cg1g2. While body-related capacitances are absent, gate-related capacitances for the second gate are added. Since total charge in the channel can be calculated analytically, these capacitances are obtained by differentiating it. Anomaly of Cg1g2 was found in the sub-threshold region when the transistor is in the double charge-sheet mode. Small change in the gate voltage causes redistribution of the carriers between two charge-sheets, while total carrier is almost unchanged. And it results in the screening current against the perpendicular electric field. This redistribution is not physics-based, and is based on the model feature. To remedy this effect, it was found that the charge-sheets should be placed at the mean position of the carriers at the source-end, instead these are placed at the silicon-insulator interface.
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