Nano Science and Technology Institute
Nanotech 2006 Vol. 3
Nanotech 2006 Vol. 3
Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3
 
Chapter 7: Compact Modeling
 

Compact Iterative Field Effect Transistor Model

Authors:M.S. Shur, V. Turin and D. Veksler, T. Ytterdal, B. IƱiguez and W. Jackson
Affilation:Rensselaer Polytechnic Institute, US
Pages:648 - 651
Keywords:thin film transistor, compact model, parameter extraction
Abstract:Compact models for field effect transistors should satisfy two conflicting requirements. On one hand, they should be simple enough and should contain a small number of physics-based parameters to be suitable for parameter extraction. On the other hand, they should accurately account for complicated device phenomena and accurately reproduce device characteristics over many orders of magnitude of the device current and for a wide range of frequencies. This latter requirement is especially important for modeling analog or mixed analog/digital circuits. We propose an iterative approach that uses a simple six-parameter model (based on Unified Charge Control Model - UCCM). This first-order approximation model accounts for the velocity saturation in the device channel, for source and drain series resistance, and for drain barrier lowering. The Universal Current Model (UCM) is used for the output current-voltage characteristics. This model is suitable for parameter extraction and allows for excellent conversion even at very small feature sizes because of the continuity of all derivatives of the current and voltage with respect to extrinsic gate and drain voltages. The drain barrier lowering in the UCCM avoids fictitious nonlinearities, a constant slope of the current as a function of the extrinsic drain-to-source voltage, predicted by the conventional model. The new model is augmented by the unified Meyers capacitance model that accounts for capacitance dispersion at high frequencies via Elmore constants. Using this model, we derive the intrinsic drain and gate bias and corresponding drain current and gate-to-source and gate-to-drain capacitance. These values are used for the second iteration model to account for such effects as the channel mobility dependence on the intrinsic gate and drain biases.
Compact Iterative Field Effect Transistor ModelView PDF of paper
ISBN:0-9767985-8-1
Pages:913
Hardcopy:$119.95
 
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