 | Nanotech 2006 Vol. 3
Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 7: Compact Modeling |
| - | Symbolic charge-based MOSFET model |
| | C. Galup-Montoro and M.C. Schneider |
| | Federal University of Santa Catarina, BR |
| - | Theory and Modeling Techniques used in PSP Model |
| | G. Gildenblat, X. Li, H. Wang, W. Wu, A. Jha, R. van Langevelde, A.J. Scholten, G.D.J. Smit and D.B.M. Klaassen |
| | Pennsylvania State University, US |
| - | An Improved MOS Transistor Model with an Integrated Mobility Model |
| | J.R. Hauser |
| | N.C. State University, US |
| - | Benchmark Tests on Conventional Surface Potential Based Charge-Sheet Models And the Advanced PUNSIM Development |
| | J. He, Y. Song, X. Niu, G. Zhang, X. Zhang, R. Huang, M. Chan and Y. Wang |
| | Peking university, CN |
| - | Accuracy of Surface-Potential-Based Long-Wide-Channel MOS Transistor Compact Models |
| | B.B. Jie and C-T Sah |
| | University of Florida, US |
| - | Advanced Compact MOSFET Model HiSIM2 Based on Surface Potentials with a Minimum Number of Approximation |
| | M. Miura-Mattausch, D. Navarro, N. Sadachika, G. Suzuki, Y. Takeda, M. Miyake, T. Warabino, K. Machida, T. Ezaki, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, R. Inagaki and S. Miyamoto |
| | Hiroshima University, JP |
| - | Halo Doping: Physical Effects and Compact Modeling |
| | S. Mudanai, R. Rios, W-K Shih, P. Packan and S-W Lee |
| | Intel Corp., US |
| - | Compact Iterative Field Effect Transistor Model |
| | M.S. Shur, V. Turin and D. Veksler, T. Ytterdal, B. Iñiguez and W. Jackson |
| | Rensselaer Polytechnic Institute, US |
| - | Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling |
| | X. Zhou, K. Chandrasekaran, S.B. Chiah, W. Shangguan, Z. Zhu, G.H. See, S. Mani Pandey, G.H. Lim, S. Rustagi, M. Cheng, S. Chu and L-C Hsia |
| | Nanyang Technological University, SG |
| - | BSIM4 and BSIM Multi-Gate Progress |
| | M.V. Dunga, C.–H. Lin, X. Xi, S. Chen, D.D. Lu, A.M. Niknejad and C. Hu |
| | UC Berkeley, US |
| - | A Charge-Based Compact Model of Double Gate MOSFET |
| | A.S. Roy, C.C. Enz and J.M. Sallese |
| | CSEM, CH |
| - | Precise 2D Compact Modeling of Nanoscale DG MOSFETs Based on Conformal Mapping Techniques |
| | T.A. Fjeldly, S. Kolberg and B. Iñíguez |
| | Norwegian University of Science and Technology, NO |
| - | Recent Upgrades and Applications of UFDG |
| | J.G. Fossum, V.P. Trivedi, M.M. Chowdhury, S.H. Kim and W. Zhang |
| | University of Florida, US |
| - | DC to RF Small-Signal Compact DG MOSFET model |
| | B. Iñíguez, A. Lázaro, O. Moldovan, A. Cerdeira and T.A. Fjeldly |
| | Universitat rovira i Virgili (URV), ES |
| - | An Explicit Quasi-Static Charge-Based Compact Model for Symmetric DG MOSFET |
| | F. Prégaldiny, F. Krummenacher, J.-M. Sallese, B. Diagne and C. Lallement |
| | InESS, FR |
| - | On the Modeling of the Current-Voltage Characteristics of a Symmetrical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with an Undoped Body |
| | M. Wong and X. Shi |
| | Hong Kong University of Science and Technology, HK |
| - | Device Correlation: Modeling using Uncorrelated Parameters, Characterization Using Ratios and Differences |
| | C.C. McAndrew and P.G. Drennan |
| | Freescale Semiconductor, US |
| - | Modeling Small MOSFETs using Ensemble Devices |
| | J.S. Watts, R. Pino and H. Trombley |
| | IBM, US |
| - | Effects of Scaling on Modeling of Analog RF MOS Devices |
| | Y. Liu, S. Cao, T.Y. Oh, B. Wu, O. Tornblad and R.W. Dutton |
| | Stanford University, US |
| - | High-Voltage LDMOS Compact Modeling |
| | M.B. Willemsen, R. van Langevelde and D.B.M. Klaassen |
| | Philips Research, NL |
| - | Analog Compact Modeling for a 20-120V HV CMOS Technology |
| | E. Seebacher, W. Posch, K. Molnar and Z. Huszka |
| | austriamicrosystems AG, AT |
| - | Compact Modeling of Spiral Inductors for RF Applications |
| | J. Chen and J.J. Liou |
| | University of Central Florida, US |
| - | Development and Design Kit Integration of a Scalable and Statistical High Current Model for Advanced SiGe HBTs |
| | R.M. Malladi, K.M. Newton and M.S. Schroter |
| | IBM Systems and Technology, US |
| - | Charge-storage calculation for Si-based bipolar transistors from device simulation |
| | M. Schröter and H. Tran |
| | UCSD, US |
| - | Compact Modeling of Short Channel Double-Gate MOSFETs |
| | H. Lu, X. Liang, W. Wang and Y. Taur |
| | Univ. California, San Diego, US |
| - | DC and AC Symmetry Tests for MOSFET Models |
| | C.C. McAndrew |
| | Freescale Semiconductor, US |
| - | Scalable MOSFET Short-channel Charge Model in All Regions |
| | G.H. See, S.B. Chiah, X. Zhou, K. Chandrasekaran, W. Shangguan, Z. Zhu, G.H. Lim, S.M. Pandey, M. Cheng, S. Chu and L-C Hsia |
| | NTU, SG |
| - | Compact Modeling of Nonlinearities in Submicron MOSFETs |
| | P.D. da Silva, F.R. de Sousa, C.G. Montoro and M.C. Schneider |
| | Federal University of Santa Catarina, BR |
| - | On the Compact Modelling of Induced Gate Noise in the MOS Transistor |
| | A.S. Roy and C.C. Enz |
| | Swiss Federal Institute of Technology, Lausanne (EPFL), CH |
| - | Comprehensive Characterization and Analysis of RTS, 1/f, RF Noise and Power Performances of Schottky-Diode in Standard CMOS |
| | Y.Z. Xiong, G.Q. Lo, J.L. Shi, M.B. Yu, W.Y. Loh and D.L. Kwong |
| | Institute of Microelectronics, Singapore, SG |
| - | Two-Tone Distortion Modeling for SiGe HBTs Using the High-Current Model |
| | R.R. Malladi, V. Borich, S.L. Sweeney, J. Rascoe, K.M. Newton, S. Venkatadri, J. Yang and S. Chen |
| | IBM Systems and Technology, US |
| - | BSIM Model for MOSFET Flicker Noise Statistics: Technology Scaling, Area, and Bias Dependence |
| | M. Ertürk, R. Anna, K.M. Newton, T. Xia and W.F. Clark |
| | IBM Systems and Technology Group, US |
| - | Investigation of Substrate Current Effects and Modeling of Substrate Resistance Network for RFCMOS |
| | J.C. Lee, R.B. Anna, S.L. Sweeney, L.H. Pan and K.M. Newton |
| | IBM Corporation, US |
| - | TCAD-based Process Dependant HSPICE Model Parameter Extraction |
| | Y. Mahotin, S. Tirumala, X-W Lin and D. Pramanik |
| | Synopsys, Inc., US |
| - | Analysis and Modeling of NQS Effects in MOSFET’s |
| | Y. Ma, M-C Jeng, H. Liang and Z. Liu |
| | Cadence Design Systems, Inc., US |
| - | Compact Capacitance Model of LDMOS for Circuit Simulation |
| | Y. Ma, P. Chen, H. Liang, J. Ma, M-C Jeng and Z. Liu |
| | Cadence Design Systems, Inc., US |
| - | A Carrier Based Analytic Model for Undoped Surrounding-Gate MOSFETs |
| | J. He, X. Zhang, M. Chan and Y. Wang |
| | Peking university, CN |
| - | Compact Modeling of Doped Symmetric DG MOSFETs with Regional Approach |
| | K. Chandrasekaran, Z.M. Zhu, X. Zhou, W. Shangguan, G.H. See, S.B. Chiah, S.C. Rustagi and N. Singh |
| | Nanyang Technological University, SG |
| - | Explicit Threshold Voltage Based Compact Model of Independent Double Gate MOSFET |
| | M. Reyboz, T. Poiroux, O. Rozeau, P. Martin and J. Jomaah |
| | CEA, FR |
| - | Capacitance Model for Four-Terminal DG MOSFETs |
| | T. Nakagawa, T. Sekigawa, T. Tsutsumi, M. Hioki, S. O’uchi and H. Koike |
| | National Institute of Advanced Industrial Science and Technology, JP |
| - | A Computationally Efficient Method for Analytical Calculation of Potentials in Undoped Symmetric DG SOI MOSFET |
| | O. Cobianu and M. Glesner |
| | Darmstadt University of Technology, DE |
| - | Compact Model of drain-current in Double-Gate MOSFETs including carrier quantization and short-channel effects |
| | X. Loussier, D. Munteanu, J.L. Autran, S. Harrison and R. Cerutti |
| | L2MP, FR |
| - | Compact modeling and performance analysis of Double-Gate MOSFET-based circuits |
| | O. Tintori, D. Munteanu, X. Loussier, J.L. Autran, A. Regnier and R. Bouchakour |
| | L2MP, FR |
| - | Comparison of Three Region Multiple Gate Nanoscale Structures for Reduced Short Channel Effects and High Device Reliability |
| | K. Goel, M. Saxena, M. Gupta and R.S. Gupta |
| | Professor, IN |
| - | Compact Model for Short Channel Effects in Source/Drain Engineered Nanoscale Double Gate (DG) SOI MOSFETs |
| | A. Kranti and G.A. Armstrong |
| | Queen’s University of Belfast, UK |
| - | Compact Models for Double Gate and Surrounding Gate MOSFETs |
| | H. Abebe, E. Cumberbatch, H. Morris and S. Uno |
| | San Jose State University, US |
| - | SOI CMOS Compact Modeling based on TCAD Device Simulations |
| | A. Botula, S. Furkay, D.C. Sheridan, J.M. Johnson and M-H Na |
| | IBM Corporation, US |
| - | On Idlow with Emphasis on Speculative SPICE Modeling |
| | Q. Chen, Z-Y Wu, A.B. Icel, J-S Goo, S. Krishnan, C. Thuruthiyil, N. Subba, S. Suryagandh, J.X. An, T. Ly, M. Radwin, J. Yonemura and F. Assad |
| | Advanced Micro Devices, US |
| - | Dynamic Behavior Model for High-k MOSFETs |
| | M.V. Dunga, X. Xi, A.M. Niknejad and C. Hu |
| | University of California, Berkeley, US |
| - | A Simple Yet Accurate Mismatch Model For Circuit Simulation |
| | Z. Jin, Y-M Lee, J.S. Watts, A.R. Bonaccio, G.J. Schroer and N.G. Pai |
| | IBM, US |
| - | Enhanced Junction Capacitance Modeling |
| | F.G. Anderson, R.M. Rassel and M.A. Lavoie |
| | IBM Microelectronics, US |
| - | A Compact Model of Ballistic CNFET for Circuit Simulation |
| | B.C. Paul, S. Fujita, M. Okajima and T. Lee |
| | Toshiba America Research Inc., US |
| - | A Circuit-Compatible Model for Ballistic Silicon Nanowire Transistors |
| | J. Chen |
| | Agere Systems, US |
| - | Compact Modeling of Threshold Voltage in Nanoscale Strained-Si/SiGe MOSFETs |
| | S. Nawal, V. Venkataraman and M.J. Kumar |
| | Indian Institute of Technology, IN |
| - | Compact Model Methodology for Dual-Stress Nitride Liner Films in a 90nm SOI ULSI Technology |
| | R.Q. Williams, D. Chidambarrao, J.H. McCullen, S. Narasimha, T.G. Mitchell and D. Onsongo |
| | IBM Corporation, US |
| - | A transient circuit model for a phase change memory element |
| | H.G.A. Huizing, D. Tio Castro, J.C.J. Paasschens and M.H.R. Lankhorst |
| | Philips, NL |
| - | Static Analog Design Methodology |
| | F. Guigues, F. Rudolff and E. Kussener |
| | L2MP UMR 6137 CNRS - ISEN-Toulon, FR |
| - | Interrelations between Threshold Voltage Definitions and Extraction Methods |
| | M.C. Schneider, C. Galup-Montoro, M.B. Machado and A.I.A. Cunha |
| | Federal University of Santa Catarina, BR |
| - | A Unified Parameter Extraction Procedure for Scalable Bipolar Transistor Model Mextram |
| | H-C Wu, S. Mijalkovic and J.N. Burghartz |
| | Delft university of technology, NL |
| - | Charge-Based Formulation of Thermal Noise in Short-Channel MOS Transistors |
| | V.C. Paim, C. Galup-Montoro and M.C. Schneider |
| | Federal University of Santa Catarina, BR |
| ISBN: | 0-9767985-8-1 |
| Pages: | 913 |
| Hardcopy: | $185.00 |
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