Nano Science and Technology Institute
Nanotech 2006 Vol. 1
Nanotech 2006 Vol. 1
Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 1
 
Chapter 7: Nanoscale Modeling
 

VHDL Simulation considering Single Event Upsets (SEUs)

Authors:M. Grecki
Affilation:Technical University of Lodz, PL
Pages:717 - 720
Keywords:SEU, VHDL, simulation
Abstract:The SEEs can be destructive for semiconductor devices, however non-destructive SEE called SEU ( Single Event Upsets) resulting of bit flips seems to be the main problem. Due to reduction of feature size the SEUs play an increasing role in failures observed during operation of digital circuits, particularly in environments with remarkable radiation level (avionics, nuclear industry, High Energy Physics instrumentation etc.). The special design methods, based on hardware and software redundancy, allow to detect and correct radiation influenced SEUs during system operation, making such a system radiation-tolerate.
This paper presents the SEUSIM software library and method of VHDL model conversion that allow to simulate the operation of digital circuit taking into account SEUs. The library is written in pure VHDL so it can be used by most VHDL simulators.
The simulation example concerns the control system applied in RadMon neutron detector. The simulation results well correspond to the data calculated from mathematical model of SEU occurrence. The simulation considering SEUs can be used in design of radiation tolerate circuits.
VHDL Simulation considering Single Event Upsets (SEUs)View PDF of paper
ISBN:0-9767985-6-5
Pages:871
Hardcopy:$119.95
 
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