Nanotech 2006 Vol. 1
Nanotech 2006 Vol. 1
Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 1

Nanoscale Modeling Chapter 7

A New Grounded Lamination Gate (GLG) SOI MOSFET for Diminished Fringe Capacitance Effects

Authors: M.J. Kumar, V. Venkataraman and S.K. Gupta

Affilation: Indian Institute of Technology, India

Pages: 709 - 712

Keywords: high-K gate dielectric, threshold voltage, fringe capacitance, SOI MOSFET

Abstract:
In this paper, we propose a novel device structure, known as the Grounded Laminated Gate (GLG) SOI MOSFET to eliminate the gate fringe field effects on the threshold voltage of short channel SOI MOSFETs. Our simulaton results demonstrate that the threshold voltage roll-off with increasing dielectric constant is effectively elminated in the proposed structure.

A New Grounded Lamination Gate (GLG) SOI MOSFET for Diminished Fringe Capacitance Effects

ISBN: 0-9767985-6-5
Pages: 871
Hardcopy: $119.95