Nano Science and Technology Institute
Nanotech 2006 Vol. 1
Nanotech 2006 Vol. 1
Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 1
Chapter 7: Nanoscale Modeling

Impacts of High-k Offset Spacer on 65-nm Node SOI Devices

Authors:M-W Ma, T-S Chao, K-S Kao, J-S Huang and T-F Lei
Affilation:National Chiao Tung University, TW
Pages:697 - 700
Keywords:high-k offset spacer, SOI, fringing electric field
Abstract:In this paper, the 65-nm node SOI devices with high-k offset spacer was investigated. Calculated results show that the high-k offset spacer can effectively increase Ion and reduce Ioff due to the high vertical fringing field effect arising from the side capacitor comprising of gate/offset spacer/drain extension structure. This fringing field and, in turn, the Ion/Ioff current ratio and subthreshold swing can be strongly enhanced by increasing the dielectric constant of the offset spacer.
Impacts of High-k Offset Spacer on 65-nm Node SOI DevicesView PDF of paper
Order:Mail/Fax Form
© 2017 Nano Science and Technology Institute. All Rights Reserved.
Terms of Use | Privacy Policy | Contact Us | Site Map