Authors: J-H Lee, H-J Lee, W-H Lee, E-S Kang, J-Y Lee, K-R Byun, J-W Kang, H-J Hwang and O-K Kwon
Affilation: Sangmyung University, Korea
Pages: 343 - 346
Keywords: 90nm, parasitic resistance, TCAD, RTA
It has been reported that both the shallow junction and the heavily doped extension as the methods to minimize the off-current and to stabilize the on-current of the sub-90nm scaled device, can solve the short-channel effect and manufacturing difficulties. In this work, the performance improvement for the high speed and high performance device has been presented through the resistance study using TCAD simulation. To extract the substantial current values and quasi-fermi level in each region for the given process condition, the simulator calibration must be preceded in order that the results from the process and device simulation has the same doping level and the mobility value as those of the real device. In this paper, n/pMOS devices of which source/drain activation has been done by normal-RTA and spike-RTA, have been used as the targets of the calibration. The results from the TCAD simulation show a good agreement with the electrical characteristics of the real device, based on the comparison between the simulation and measure for correlation of Idsat versus Idoff.