Authors: A. Bindal and K. Aflatooni
Affilation: San Jose State University, United States
Pages: 244 - 247
Keywords: DRAM, nano wire, silicon wire, vertical FET
In this study, we propose a new DRAM cell that uses a silicon-wire pass transistor stacked on top of a high-dielectric capacitor rated of holding industry-standard 32 fCoulomb charge. We show that the performance of the transistor and the characteristics of the DRAM cell are comparable with those reported in the literature.