Nano Science and Technology Institute
Nanotech 2005 Vol. 3
Nanotech 2005 Vol. 3
Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
 
Chapter 3: Nano Devices and Architectures
 

The Design of a Silicon Wire DRAM Cell for Very Dense DRAM Architectures

Authors:A. Bindal and K. Aflatooni
Affilation:San Jose State University, US
Pages:244 - 247
Keywords:DRAM, nano wire, silicon wire, vertical FET
Abstract:In this study, we propose a new DRAM cell that uses a silicon-wire pass transistor stacked on top of a high-dielectric capacitor rated of holding industry-standard 32 fCoulomb charge. We show that the performance of the transistor and the characteristics of the DRAM cell are comparable with those reported in the literature.
The Design of a Silicon Wire DRAM Cell for Very Dense DRAM ArchitecturesView PDF of paper
ISBN:0-9767985-2-2
Pages:786
Hardcopy:$109.95
 
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