 | Nanotech 2005 Vol. 3
Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 3: Nano Devices and Architectures |
Room-Temperature InAlAs/InGaAs Planar Tunneling-coupled Transistor | |
| Authors: | J.S. Moon, R. Rajavel, D. Chow, S. Bui and D. Wong |
| Affilation: | HRL Labs, US |
| Pages: | 207 - 208 |
| Keywords: | tunneling, nano, transistor, room-temperature |
| Abstract: | In this talk, we report the first experimental demonstration of InAlAs/InGaAs planar tunneling-coupled transistors at room temperature, in which tunneling characteristics such as negative differential resistance (NDR) and peak current are controlled with high gain and transconductance by a surface Schottky gate similar to state-of-the-art HEMTs. Functionality of the device can be switched between HEMT mode and tunneling transistor mode. The fabrication process is fully compatible with conventional HEMT processes, offering a fully integrable and scalable tunneling transistor technology. The planar tunneling-coupled transistors were fabricated with closely-coupled dual-channel HEMT heterostructures based on InGaAs/InAlAs/InP or InGaAs/InAlAs/AlAs/InP structures by providing independent electrical contacts to each HEMT channel. The fabrication process was done using an I-line Cannon stepper on full 3-inch wafers with implanted back-gates defined prior to MBE growth of closely-coupled dual-channel HEMT layers. The mobility is typically 9600 cm2/Vs at room temperature. With AlAs/AlGaAs/AlAs or AlGaAs/AlAs/AlGaAs tunneling barriers, room-temperature peak-to-valley current ratio (PVR) is 5:1. The peak current density is 2.4 x 103 A/cm2 per gate area over 7.5 nm barrier. We will show gate-voltage induced switching of tunneling current with high gain and speed. |
 | View PDF of paper |
| ISBN: | 0-9767985-2-2 |
| Pages: | 786 |
| Hardcopy: | $109.95 |
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