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 | Nanotech 2005 Vol. 3
Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 2: CNT, Nano and Molecular Electronics |
| | Novel Nonvolatile Logic Circuits with Three-Dimensionally Stacked Nanoscale Memory Device | | Authors: | K. Abe, S. Fujita and T.H. Lee | | Affilation: | Toshiba Corporation, JP | | Pages: | 203 - 206 | | Keywords: | emerging memory, 3D stacking, nonvolatile logic circuit | | Abstract: | Various emerging memories have been proposed for ultra high-density memory, such as phase change memory, organic memory or resistive memory. However, the potential of the emerging memories is not limited to RAM only. We have proposed that, by 3D stacking emerging memory on CMOS, logic circuits can be embedded in local interconnect, thereby enabling small area and low power consumption. D-type flip flop (D-F/F) is most frequently used as sequential logic circuits. We propose the nonvolatile D-F/F using emerging memory. The nonvolatile D-F/F consists of 3D stacked emerging memory and reference resistance connected in series with slave side cross-coupled inverters. Since the data is stored in emerging memory, supply voltage can be shut down to the unused logic block. To recall the stored data, the node voltage of output is determined by the RC delay depending on the resistance of emerging memory and reference. We demonstrate the recall operation by SPICE simulation. As a result the most feasible emerging memory is the resistive memory. By using these memories, small logic circuits with low power consumption can be realized. Such novel circuit design is much effective especially for FPGA consisting of a lot of D-type flip flops. | | ISBN: | 0-9767985-2-2 |
| Pages: | 786 |
| Hardcopy: | $165.00 |
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