Nano Science and Technology Institute
Nanotech 2005 Vol. 3
Nanotech 2005 Vol. 3
Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
 
Chapter 10: Computational Methods, Numerics and Software Tools
 

A Parallel Intelligent OPC Technique for Design and Fabrication of VLSI Circuit

Authors:S-M Yu and Y. Li
Affilation:National Chiao Tung University, TW
Pages:724 - 727
Keywords:parallel computing, intelligent algorithm, OPC, fabrication, design, VLSI
Abstract:Optical lithography is the key technology used in very large scale integrated (VLSI) circuit and systemon- a-chip (SoC) fabrication [1-3]. The exposure on wafer has distortions due to the proximity effects. Hence, a correction of mask patterns between circuit and post exposure result is necessary for obtaining a better agreement. Optical proximity correction (OPC) [1-3] is the process of modifying the polygons that are drawn by designers to compensate for the non-ideal properties of the lithography process. During the OPC process, it is always applied lithography simulation to evaluate the modified layouts. Unfortunately, whole system’s lithography simulation is time-consuming and requires large computational resource [1-3]. We in this paper propose a parallel intelligent OPC technique for process distortion compensation of layout mask. It combines am improved genetic algorithm (GA) [3], the rule- and model-based methods [2-3], and static domain decomposition algorithm [3] to perform the mask correction on a Linux-based PC cluster with MPI libraries [3]. Basic idea is that we apply the GA and the lithography simulator to optimize those additional patterns which generated by rules for counteracting the imaging effect that now distorts patterns on the wafer. First of all, an original layout is partition into several sub-domains with the domain decomposition method. It estimates each pattern’s size and amounts of all patterns in the whole layout domain, and dispatches suitable patterns to each sub-domain. Each sub-layout is then corrected with rules. Size and position for all new added patterns are optimized with respect to the calculated exposed results using the GA algorithm. The exposure value is calculated with a two-dimensional lithography modeling and simulation. After OPC procedures, each corrected layouts for all sub-domains are combined into a complete mask. To reduce the inconsistence of layout combination, there are suitable overlaps between neighbor sub-domains. When merging two neighbor sub-domains, we estimate and compare the error norm of different sub-domains in the overlaps, and then select the corrected layouts with the smaller error norms in overlaps as the final results. This method can overcome the inconsistent situation in the overlaps and get the better corrected results. Fig. 1 shows a tested fundamental layout pattern without applied any resolution correction and the simulation exposed image. It is obvious that there are some distortions between original layout and aerial image in each corner. Fig. 2 shows the OPC corrected results and the distortions are improved. Fig. 3 shows a part of a SoC layout which corrected by the proposed parallel OPC method. The examined layout contains more than four thousand fundamental patterns and takes about 8 hours to finish OPC in a 16 nodes PC cluster with 2 GHz CPU and 512 MB RAM. Very good parallel performance and speedup are obtained in this novel computational technique..
A Parallel Intelligent OPC Technique for Design and Fabrication of VLSI CircuitView PDF of paper
ISBN:0-9767985-2-2
Pages:786
Hardcopy:$109.95
 
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