Nano Science and Technology Institute
Nanotech 2005 Vol. 3
Nanotech 2005 Vol. 3
Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 1: Nanoscale Device and Process Modeling

A Nano-Transistor with a Cavity

Authors:C. Ravariu, A. Rusu, M. Profirescu and F. Ravariu
Affilation:Politehnica University of Bucharest, RO
Pages:111 - 114
Keywords:SOI, MOS, SET, tunnel current, simulations, nanodevice
Abstract:A SOI nanotransistor with a cavity was simulated. The global current is a superposition of a tunnel current through the cavity and an inversion current at the film bottom. The tunnel source-drain current prevails in sub 1-nm film thickness and provides the ID-VDS characteristics with a minimum. For film thickness comprised between 100-10nm, the ID-VGS curves preserve similar shapes with a MOS/SOI transfer characteristics. For sub1-nm film thickness, the shape of the ID-VGS characteristics with a maximum suggests a SET like conduction. From the electron concentration simulations result a transport of the electrons one-by-one in the transistor body, which proves the SET like behaviour.
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