 | Nanotech 2005 Vol. 3
Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 1: Nanoscale Device and Process Modeling |
RLC Reduction Scheme for Modeling Interconnection Line Delay in nano-CMOS Circuits | |
| Authors: | C. Jung, S. Yoon and T. Won |
| Affilation: | Inha University, KR |
| Pages: | 95 - 98 |
| Keywords: | RLC-in-RLC-out, MOR, passivity, node elimination, TICER |
| Abstract: | In this paper we propose a realizable RLC-in-RLC-out technique to reduce parasitic parameters. The proposed technique is an efficient MOR (Model Order Reduction) method, which makes it possible to control the rise and delay time errors within the limit corresponding to the maximum frequency of operation. In addition, the equivalent circuit with reduced number of node elements derived from the proposed algorithm does conserve the passivity due to the use of zero-th or first order approximation. The conventional AWE, which uses the Fade’s approximation, is a well-known method and a basis for other proposed MOR methods. However, most of standard simulators are inappropriate for a very large integrated circuit due to necessity of huge amount of memory space and longer CPU time. Also, algorithms for tools such as PRIMA and RICE are complex to be implemented. The reduced circuit using the RLC-in-RLC-out technique provides faster time and lower memory, and the algorithm for reduction is easy to implement. The proposed algorithm from node elimination is based on TICER (Time Constant Equilibration Reduction) approach. |
 | View PDF of paper |
| ISBN: | 0-9767985-2-2 |
| Pages: | 786 |
| Hardcopy: | $109.95 |
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