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 | Nanotech 2005 Vol. 3
Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 1: Nanoscale Device and Process Modeling |
| | SOS Gate Capacitance Modeling | | Authors: | H.C. Morris, E.C. Cumberbatch, H. Abebe | | Affilation: | San Jose State University, US | | Pages: | 68 - 71 | | Keywords: | Capacitors, SOS, C-V characteristics, parameter extraction | | Abstract: | A gate capacitance model for the SOS structure has been developed. The spatial dependence of the potential defines the changes in the charge density as well as the boundary conditions between the layers. The SOS structure has Sapphire in the place of Insulator, SiO2 is still in between the doped Silicon (in the following calculations, the SOS device is assumed to have a P-type Silicon bulk area) and the upper layer. Both analytical and numerical aspects of the will be presented. The inverse problem, obtain device parameters from measured capacitance values, is solved and shown to provide accurate parameter estimations for real devices. New analytic formulae and numerical algorithms are presented. The model has been compared with data and performs well. | | ISBN: | 0-9767985-2-2 |
| Pages: | 786 |
| Hardcopy: | $165.00 |
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