Nano Science and Technology Institute
Nanotech 2005 Vol. 3
Nanotech 2005 Vol. 3
Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3
 
Chapter 1: Nanoscale Device and Process Modeling
 

Impact of Multi-Trap Assisted Tunneling on Gate Leakage of CMOS Memory Devices

Authors:R. Entner, A. Gehring, H. Kosina, T. Grasser and S. Selberherr
Affilation:TU-Vienna, AT
Pages:45 - 48
Keywords:CMOS, memory, dielectric, modeling, multi-trap assisted tunneling
Abstract:In this work a new approach for modeling gate leakage currents for memory cells which are highly degraded is proposed. In thicker dielectrics which are subject to high field stress and can therefore have a high defect density, not only direct tunneling currents but also trap-assisted tunneling plays an important role. By rigorous simulation we show, for the first time, that also a multi-trap assisted tunneling component becomes important for dielectric thicknesses above approximately 3 nm and even gains importance for thicker layers.
Impact of Multi-Trap Assisted Tunneling on Gate Leakage of CMOS Memory DevicesView PDF of paper
ISBN:0-9767985-2-2
Pages:786
Hardcopy:$109.95
 
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