Low Field Electron Mobility in Ultra-Thin Strained-Si Directly on Insulator MOSFET in Sub-0.1µm Regime

	Nanotech 2005 Vol. 3 Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 3 Chapter 1: Nanoscale Device and Process Modeling
	Low Field Electron Mobility in Ultra-Thin Strained-Si Directly on Insulator MOSFET in Sub-0.1µm Regime
Authors:	S. Amtablian and S. Barraud
Affilation:	CEA-DRT/LETI, FR
Pages:	37 - 40
Keywords:	FD-SOI, strained-SOI, effective mobility, quantum effect
Abstract:	A 200 word (or less) text only summThe fabrication of Fully-Depleted strained-Si directly on insulator (SSOI) MOSFET was recently demonstrated. The combination of strain-induced transport property with the scaling advantage of ultra-thin body devices is a promising way to aggressively scaled device. The motivation of this work is to developed a new low field mobility model well suited to SOI and SSOI nMOSFET with a film thickness TSOI varying from 20nm to 5nm. For the first time, a methodology based on an improved split C-V method is used to extend the effective mobility calculation in sub-0.1µm regime taking into account corrections of S-D series resistance RSD and parasitic capacitance Cp both in SOI and SSOI nMOSFET
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ISBN:	0-9767985-2-2
Pages:	786
Hardcopy:	$109.95

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