A Gate Layout Technique for Area Reduction in Nano-Wire Circuit Design

	Nanotech 2005 Vol. 2 Technical Proceedings of the 2005 NSTI Nanotechnology Conference and Trade Show, Volume 2 Chapter 7: NEMS and MEMS Fabrication
	A Gate Layout Technique for Area Reduction in Nano-Wire Circuit Design
Authors:	H. Hashempour and F. Lombardi
Affilation:	LTX Corp., US
Pages:	471 - 474
Keywords:	nanowire, circuit design, layout optimization, physical area
Abstract:	An strategy for developing integrated circuits with many individual nanodevices has yet to be formulated. This paper presents an homogeneous (array-based) approach for designing and manufacturing digital circuits using nanotubes or nanowires. By targeting contacts which occupy large area, and using a novel high level combinatorial formulation for area, substantial savings is obtained in physical mask layouts. The ultimate objective is to provide a further insight on the applicability of Moore's law to nanotechnology by evaluating the effects of area in logic circuit design.
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ISBN:	0-9767985-1-4
Pages:	808
Hardcopy:	$109.95

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