Authors: T. Wang, M. Ben-Naser, Y. Guo and C. Andras Moritz
Affilation: University of Massachusetts at Amherst, United States
Pages: 619 - 622
Keywords: nanowire, nanowires array, nanoscale circuits, streaming processors
In this paper, we describe our initial architectural designs based on nanowires (NWs). We call our initial integrated circuit systems Wire-Streaming Processors (WISP) because in these designs, in order to preserve the density advantages of nanodevices, data is streamed through the fabric with minimal control/feedback paths and intermediate values during processing are often stored on the wire without requiring explicit latching. We show detailed circuits developed on 2-D NW fabrics and show for the first time a complete 2-bit datapath and 3-bit opcode WISP design, WISP-0. We identify the challenges and show techniques to work around fabric-specific constraints. Our initial WISP-0 design successfully addresses many of the fabric-specific constraints achieving a density advantage of 40X compared to the projected 30-nm CMOS implementation. The work proposed here forms a key part of our effort to build NASICs: Nanoscale Application-Specific Integrated Circuits and it is based on extensive research on understanding emerging nanoscale device and fabrication constraints.