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 | WCM 2005
Technical Proceedings of the 2005 Workshop on Compact Modeling
Chapter 2: Poster Papers |
| | An A Priori Hysteresis Modeling Methodology for Improved Efficiency and Model Accuracy in Advanced PD SOI Technologies | | Authors: | Q. Chen, J-S Goo, N. Subba, X. Cai, J.X. An, T. Ly, Z-Y Wu, S. Suryagandh, C. Thuruthiyil, M. Radwin, L. Zamudio, J. Yonemura, F. Assad, M.M. Pelella and A.B. Icel | | Affilation: | Advanced Micro Devices, US | | Pages: | 159 - 162 | | Keywords: | SOI, hysteresis, compact modeling | | Abstract: | Exploiting the asymmetric nature of interactions among hysteresis, “nonFET”, and DC characteristics, an a priori hysteresis modeling methodology has been proposed as an essential part of an improved model extraction flow for advanced PD SOI technologies. It has been successfully implemented on a state-of-the-art 90 nm technology demonstrating projected benefits, including minimum deviation of nonFET characteristics from hardware data, improved model extraction efficiency, improved model accuracy for hysteresis over a wide range of Vdd/T, and efficient implementation of automatic hysteresis optimization. | | ISBN: | 0-9767985-3-0 |
| Pages: | 412 |
| Hardcopy: | $120.00 |
| Special: | 3 CD Set — 15% off with Free Shipping |
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