Authors: S.B. Chiah, X. Zhou, K. Chandrasekaran, G.H. See, W. Shangguan, S.M. Pandey, M. Cheng, S. Chu and L-C Hsia
Affilation: Nanyang Technological University, Singapore
Pages: 143 - 146
Keywords: drain current, threshold voltage, unified regional, geometry dependent
This paper presents calibration approach for our unified length/width-dependent MOSFET drain current (Ids) model  with the length/width-dependent threshold voltage (Vt) model  for technology characterization in the entire geometry/bias range for CMOS shallow trench isolation (STI) transistors. The model has been formulated with built-in physical effects to account for short-channel/ narrow-width effects while maintaining Gummel symmetry . Through a one-iteration parameter extraction, the model can predict accurately the experimental data from a 0.11-_m CMOS STI technology wafer.