Poster Papers

Optimized Threshold-Voltage MOS Transistor Compact Model from the 4-Component Theory

Jie B.B., Sah C-T, University of Florida, US

Based on Sah's 1996 four-component exact formula, a new optimized compact model is derived for long channel MOS transistors. This new model covers subthreshold and linear operation ranges using four independent optimization voltage parameters in [...]

All-Region MOS Model of Mismatch due to Random Dopant Placement

Klimach H., Galup-Montoro C., Schneider M.C., Universidade Federal de Santa Catarina, BR

Electron device matching has been a key factor on the performance of today’s analog or even digital electronic circuits. This paper presents a study of drain current matching in MOS transistors. A model for MOS [...]

Analog Design Tool based on the ACM model

Galup-Montoro C., Schneider M.C., dos Reis Machado C., Universidade Federal de Santa Catarina, BR

This paper presents MOSVIEW, a software tool for transistor-level analog design, which is based on the Advanced Compact MOSFET (ACM) model [1, 2], derived from physics. This tool allows rapid exploration of the design space. [...]

Extraction of Mosfet Effective Channel Length and Width Based on the Transconductance-To-Current Ratio

Cunha A.I.A., Schneider M.C., Galup-Montoro C., Caetano C.D.C., Machado M.B., Federal University of Santa Catarina, BR

This paper presents a very simple methodology for determining the effective channel length and width, which is independent of the determination of the threshold voltage. The procedure is based on measurement of the transconductance-to-current ratio [...]

Unambiguous Extraction of Threshold Voltage Based on the Transconductance-to-Current Ratio

Cunha A.I.A., Schneider M.C., Galup-Montoro C., Caetano C.D.C., Machado M.B., Federal University of Santa Catarina, BR

This paper presents a very simple methodology for determining the threshold voltage. The procedure is based on the expressions of the Advanced Compact MOSFET (ACM) model, valid in all regimes of operation, which assures physical [...]

One-Iteration Parameter Extraction for Length/width-dependent Threshold Voltage and Unified Drain Current Model

Chiah S.B., Zhou X., Chandrasekaran K., See G.H., Shangguan W., Pandey S.M., Cheng M., Chu S., Hsia L.-C., Nanyang Technological University, SG

This paper presents calibration approach for our unified length/width-dependent MOSFET drain current (Ids) model [1] with the length/width-dependent threshold voltage (Vt) model [2] for technology characterization in the entire geometry/bias range for CMOS shallow trench [...]

Unified Regional Charge-based MOSFET Model Calibration

See G.H., Chiah S.B., Zhou X., Chandrasekaran K., Shangguan W., Pandey S.M., Cheng M., Chu S., Hsia L.-C., Nanyang Technological University, SG

This paper presents a methodology to extract device physical parameters, i.e., electrical oxide thickness (tox), channel doping (Nch), and poly-gate doping (Ngate), as well as smoothing parameters in our unified regional charge-based model [1] with [...]

RF Modeling for FDSOI MOSFET and Self Heating Effect on RF Parameter Extraction

Wan H., Su P., Fung S.K.H., Dept of EECS, UC Berkeley, US

In this paper, the BSIMSOI RF model for FDSOI MOSFET is introduced and verified. Self-heating effect plays an important role in RF S-parameter fitting and the thermal resistance needs to be correctly extracted. A new [...]

The Surface-Potential-Based model HiSIM-SOI and its Application to 1/f Noise in Fully-Depleted SOI-MOSFETs

Sadachika N., Yusoff M.Md., Uetsuji Y., Bhuyan M.H., Kitamaru D., Mattausch H.J., Miura-Mattausch M., Miura-Mattausch M., Weiss L., Feldmann U., Baba S., Graduate School of Advanced Sciences of Matter, Hiroshima University, JP

Fully-depleted SOI-MOSFET model HiSIM-SOI for circuit simulation is developed. HiSIM-SOI solves surface potentials at all three SOI-surfaces along the depth direction self-consistently. Besides comparison to measured I-V characteristics, the model is verified with 1/f noise [...]

An A Priori Hysteresis Modeling Methodology for Improved Efficiency and Model Accuracy in Advanced PD SOI Technologies

Chen Q., Goo J-S, Subba N., Cai X., An J.X., Ly T., Wu Z-Y, Suryagandh S., Thuruthiyil C., Radwin M., Zamudio L., Yonemura J., Assad F., Pelella M.M., Icel A.B., Advanced Micro Devices, US

Exploiting the asymmetric nature of interactions among hysteresis, “nonFET”, and DC characteristics, an a priori hysteresis modeling methodology has been proposed as an essential part of an improved model extraction flow for advanced PD SOI [...]

SPICE Modeling of Multiple Correlated Electrical Effects of Dopant Fluctuations

Lee Y.M., Watts J., Grundon S., Cook D., Howard J., IBM Semiconductor Research and Developement Center, US

We proposed a new methodology capable of accurately modeling the partial correlations and geometric dependency in the local random fluctuations of various electrical parameters. This method incorporates principal factor analysis (PFA) into the conventional SPICE-based [...]

A Compact Physical Model for Critical Quantum Mechanical Effects On MOSFET

Wang L., Meindl J.D., Georgia Institute of Technology, US

As the MOSFET is scaled down to sub-100nm range, two quantum mechanical effects (QME) of the energy quantization and the electron tunneling though the gate oxide become critical. A new compact physical model for QME [...]

A Compact Model to Predict Quantized Sub-Band Energy Levels and Inversion Layer Centroid of MOSFET with Parabolic Potential Well Approximation

He J., Chan M., Hu C., University of California-Berkeley, US

A novel analytical model to predict the sub-band energy levels and inversion charge centroid in MOS surface inversion layer with the parabolic potential well approximation has been presented in this paper. Based on coupled solution [...]

A Compact Model for the Threshold Voltage of Silicon Nanowire MOS Transistors including 2D-Quantum Confinement Effects

Nehari K., Autran J-L, Munteanu D., Bescond M., L2MP-CNRS, FR

A quantum-mechanical compact model of the threshold voltage for quantum-wire (QW) MOSFETs has been developed. This approach is based on analytical 2D solutions for the decoupled Schrödinger and Poisson equations solved in a 2D cross-section [...]

Compact Modeling of Threshold Voltage in Double-Gate MOSFET including Quantum Mechanical and Short Channel Effects

Nehari K., Munteanu D., Autran J-L, Harrison S., Tintori O., Skotnicki T., L2MP-CNRS, FR

Compact modeling of Double-Gate MOSFET incites very much interest presently, since DG is considered to be the best candidate for the integration at the end-of-roadmap. The aim of this work is to develop a short-channel [...]

Compact Model for Ultra-Short Channel Four-Terminal DG MOSFETs for Exploring Circuit Characteristics

Nakagawa T., Sekigawa T., Tsutsumi T., Hioki M., Suzuki E., Koike H., National Institute of Advanced Industrial Science and Technology (AIST), JP

We have proposed a compact model of the DG MOSFETs which handles two gates independently. The model can simulate the DG MOSFETs of asymmetric gate design, together with their four-terminal operation. In this report, we [...]

Device Parameter Extraction from Fabricated Double-Gate MOSFETs

Tsutsumi T., Liu Y., Nakagawa T., Sekigawa T., Hioki M., Suzuki E., Koike H., National Institute of Advanced Industrial Science and Technology (AIST), JP

Accurate spice simulation needs parameter extraction of the fabricated DG-MOSFETs with good electrical characteristics. However, it is very difficult to fabricate such good DG-MOSFETs, so that device parameter extraction of the fabricated DG-MOSFETs has been [...]

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