Poster Papers

	WCM 2005 Technical Proceedings of the 2005 Workshop on Compact Modeling Chapter 2: Poster Papers
-	Optimized Threshold-Voltage MOS Transistor Compact Model from the 4-Component Theory
	B.B. Jie and C-T Sah
	University of Florida, US
-	All-Region MOS Model of Mismatch due to Random Dopant Placement
	H. Klimach, C. Galup-Montoro and M.C. Schneider
	Universidade Federal de Santa Catarina, BR
-	Analog Design Tool based on the ACM model
	C. Galup-Montoro, M.C. Schneider and C. dos Reis Machado
	Universidade Federal de Santa Catarina, BR
-	Extraction of Mosfet Effective Channel Length and Width Based on the Transconductance-To-Current Ratio
	A.I.A. Cunha, M.C. Schneider, C. Galup-Montoro, C.D.C. Caetano and M.B. Machado
	Federal University of Santa Catarina, BR
-	Unambiguous Extraction of Threshold Voltage Based on the Transconductance-to-Current Ratio
	A.I.A. Cunha, M.C. Schneider, C. Galup-Montoro, C.D.C. Caetano and M.B. Machado
	Federal University of Santa Catarina, BR
-	One-Iteration Parameter Extraction for Length/width-dependent Threshold Voltage and Unified Drain Current Model
	S.B. Chiah, X. Zhou, K. Chandrasekaran, G.H. See, W. Shangguan, S.M. Pandey, M. Cheng, S. Chu and L-C Hsia
	Nanyang Technological University, SG
-	Unified Regional Charge-based MOSFET Model Calibration
	G.H. See, S.B. Chiah, X. Zhou, K. Chandrasekaran, W. Shangguan, S.M. Pandey, M. Cheng, S. Chu and L-C Hsia
	Nanyang Technological University, SG
-	RF Modeling for FDSOI MOSFET and Self Heating Effect on RF Parameter Extraction
	H. Wan, P. Su and S.K.H. Fung
	Dept of EECS, UC Berkeley, US
-	The Surface-Potential-Based model HiSIM-SOI and its Application to 1/f Noise in Fully-Depleted SOI-MOSFETs
	N. Sadachika, M.Md. Yusoff, Y. Uetsuji, M.H. Bhuyan, D. Kitamaru, H.J. Mattausch, M. Miura-Mattausch, L. Weiss, U. Feldmann and S. Baba
	Graduate School of Advanced Sciences of Matter, Hiroshima University, JP
-	An A Priori Hysteresis Modeling Methodology for Improved Efficiency and Model Accuracy in Advanced PD SOI Technologies
	Q. Chen, J-S Goo, N. Subba, X. Cai, J.X. An, T. Ly, Z-Y Wu, S. Suryagandh, C. Thuruthiyil, M. Radwin, L. Zamudio, J. Yonemura, F. Assad, M.M. Pelella and A.B. Icel
	Advanced Micro Devices, US
-	SPICE Modeling of Multiple Correlated Electrical Effects of Dopant Fluctuations
	Y.M. Lee, J. Watts, S. Grundon, D. Cook and J. Howard
	IBM Semiconductor Research and Developement Center, US
-	A Compact Physical Model for Critical Quantum Mechanical Effects On MOSFET
	L. Wang and J.D. Meindl
	Georgia Institute of Technology, US
-	A Compact Model to Predict Quantized Sub-Band Energy Levels and Inversion Layer Centroid of MOSFET with Parabolic Potential Well Approximation
	J. He, M. Chan and C. Hu
	University of California, Berkeley, US
-	A Compact Model for the Threshold Voltage of Silicon Nanowire MOS Transistors including 2D-Quantum Confinement Effects
	K. Nehari, J.L. Autran, D. Munteanu and M. Bescond
	L2MP-CNRS, FR
-	Compact Modeling of Threshold Voltage in Double-Gate MOSFET including Quantum Mechanical and Short Channel Effects
	K. Nehari, D. Munteanu, J.L. Autran, S. Harrison, O. Tintori and T. Skotnicki
	L2MP-CNRS, FR
-	Compact Model for Ultra-Short Channel Four-Terminal DG MOSFETs for Exploring Circuit Characteristics
	T. Nakagawa, T. Sekigawa, T. Tsutsumi, M. Hioki, E. Suzuki and H. Koike
	National Institute of Advanced Industrial Science and Technology (AIST), JP
-	Device Parameter Extraction from Fabricated Double-Gate MOSFETs
	T. Tsutsumi, Y. Liu, T. Nakagawa, T. Sekigawa, M. Hioki, E. Suzuki and H. Koike
	National Institute of Advanced Industrial Science and Technology (AIST), JP
-	A Compact I-V Model for FinFETs Comprising Multi-Dimensional Electrostatics and Quantum Mechanical Effects
	D. Zhang, Z. Yu and L. Tian
	Tsinghua University, CN
-	How To Design for Analog Yield using Monte Carlo Mismatch SPICE Models
	P.B.Y. Tan, A.V. Kordesch and O. Sidek
	Silterra Malaysia Sdn Bhd, MY
-	Modeling Snapback and Rise-time Effects in TLP Testing for ESD MOS Devices using BSIM3 and VBIC Models
	Y. Zhou, D. Connerney, R. Carroll and T. Luk
	Fairchild Semiconductor, US
-	Airgap and Line Slope Modeling for Interconnect
	F. Badrieh and H. Puchner
	Cypress Semiconductor, US
-	HiSIM-1.2: The Effective Gate Length Validation with the Capacitance Data
	Y. Iino
	Silvaco Japan, JP
-	An Optimization Method of Deep Submicron SOI Compact Model Parameter Extraction
	Y. Mahotin and R. Mickevicius
	Synopsys, Inc., US
ISBN:	0-9767985-3-0
Pages:	412
Up