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 | WCM 2005
Technical Proceedings of the 2005 Workshop on Compact Modeling
Chapter 1: Invited Papers |
| | Modeling FET Variation Within a Chip as a Function of Circuit Design and Layout Choices | | Authors: | J. Watts, N. Lu, C. Bittner, S. Grundon and J. Oppold | | Affilation: | IBM, US | | Pages: | 87 - 92 | | Keywords: | FET variation modeling, circuit design, layout choices, compact modeling | | Abstract: | In addition to the overall range of circuit characteristics expected from process variation the circuit designer needs to know how closely different circuit element will track one another. We describe a new methodology for modeling correlation between the chip mean variation different design FET and between different FET instances on a single chip. In addition it enables modeling the impact of circuit design choices on FET and circuit tracking. | | ISBN: | 0-9767985-3-0 |
| Pages: | 412 |
| Hardcopy: | $120.00 |
| Special: | 3 CD Set — 15% off with Free Shipping |
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