Authors: N.D. Arora and L. Song
Affilation: Cadence Design Systems, United States
Pages: 46 - 51
Keywords: high frequency effect, on chip interconnect, delay, crosstalk, ground bounce
This paper discusses the accurate modeling of resistance R, inductance L and capacitance C in sub-100nm process node and their impacts on high frequency effects such as delay, crosstalk, and power/ground bounce. Models of interconnect (wire) resistances increase due to electron scattering at the surface and grain boundaries, and coupling capacitance of high aspect ratio interconnects for sub- 100nm process nodes are presented. It is observed from test chip measurement that the skin effect and inductive effects of Cu interconnect at high frequencies exhibit different behaviors compared to Al interconnect, presumably because of the presence of CMP dummy metal fills. It is shown that the incorporation of frequency dependent R and L is essential in the modeling and characterization of high frequency effects for high speed ULSI circuits.