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 | Nanotech 2004 Vol. 3
Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 4: Nano Devices and Systems |
| | On the Design of SET Adders | | Authors: | M. Sulieman and V. Beiu | | Affilation: | Washington State University, US | | Pages: | 169 - 172 | | Keywords: | single-electron technology, threshold logic, adders | | Abstract: | Single-Electron-Technology (SET) is one of the future technologies distinguished by its small and low power devices. Among others, SET provides simple and elegant solutions for implementing threshold logic gates (TLG).One of the SET-TLG logic circuits which was presented in several recent studies is the classical full adder. The focus of these reports has been on a single-bit adder (full adder), and only a few articles extend it to multi-bit adders. Even more, such extensions used simple adder structures, and investigations of advanced adder architectures was left open. At the gate level, the capacitive-input SET inverter (C-SET) lends itself well to the design of TLGs. It was used to design majority gates (which are special TLGs having all weights equal to 1).This paper will generalize the design to arbitrary TLGs and provide a detailed procedure for designing C-SET TLGs. The application of this procedure to the design of a 16-bit parallel-prefix adder will also be described. In the literature about SET, power dissipation was only investigated for single gates (inverters), and was never reported for larger systems. In this paper we shall present and discuss both the delay and the power dissipation of our novel adder. | | ISBN: | 0-9728422-9-2 |
| Pages: | 561 |
| Hardcopy: | $150.00 |
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