| |
 | Nanotech 2004 Vol. 3
Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 3
Chapter 4: Nano Devices and Systems |
| | Silicon Nanostructures Patterned on SOI by AFM Lithography | | Authors: | I. Ionica, L. Montès, S. Ferraton, J. Zimmermann, V. Bouchiat and L. Saminadayar | | Affilation: | IMEP-INPGrenoble, GF | | Pages: | 165 - 168 | | Keywords: | AFM lithography, SOI, nano-wire, background charges, electrical characterisation, simulation | | Abstract: | The actual trends in microelectronics are the reduction of the dimensions and the search of new devices standing upon new phenomena as in the case of a Single Electron Transistor (SET) that is based on the Coulomb blockade effect. The nowadays limitation for devices dimensions is that we are reaching the resolution limits of conventional lithography techniques. Upon the new proposed routes, Atomic Force Microscope (AFM) lithography [1] is one of the most promising, because of the very good resolution that can be obtained (less than 10nm, with improvement capabilities when using carbon nanotubes) and it is fully compatible with CMOS technology. In addition, the use of silicon-on-insulator (SOI) as a substrate ensures reproducible devices with very thin monocrystalline films (15nm) and having good interface quality. We use devices fabricated on SOI by AFM lithography in applications like multi-gate transistors and monoelectronic devices such as SETs in order to study the influence of the background and interface charges. The principle of the fabrication rely on the controlled local AFM oxidation of the top SOI layer between two contact plots, followed by appropriate etching of the remaining silicon. Thus we obtain silicon nano-wires (Fig.1) without using masks, without having proximity effects and without introducing electrostatic charges in the active layer during the lithography. The electronic transport in the wire is controlled by the lateral gates and by the back-gate (the substrate). In the ohmic region the current flowing in the wire has a linear dependence of the bias applied across the wire. In addition to that, the wire conductance is well controlled by the back-gate bias (Fig.2). The important role of surface states for the conduction through a wire with such dimensions is evidenced and discussed by comparing our experimental results with simulations obtained with a commercial simulator, SILVACO, as shown in Fig.3. Different chemical and thermal post-treatments are discussed to further improve the electrical characteristics of the devices, based on both experimental and simulation results. References : [1] N. Clement, D. Tonneau, H. Dallaporta, V. Bouchiat, D. Fraboulet, D. Mariole, J. Gautier, V. Safarov, Electronic transport properties of single-crystal silicon nanowires fabricated using an atomic force microscope., Physica E, 13(2-4), pp. 999-1002, (2002) [2] H. F. Okorn-Schmidt, Characterization of silicon surface preparation processes for advanced gate dielectrics. IBM Journal of Research and Development, 43(3), pp. 351-65 (1999). | | ISBN: | 0-9728422-9-2 |
| Pages: | 561 |
| Hardcopy: | $150.00 |
|
| Order: | Mail/Fax Form |
| Special: | 3 CD Set — 15% off with Free Shipping |
| Up | |
|
| nanoPRwire™ |
 |
| News Headlines |
 |
|
|
| |
| |
|
| | |
| |
|
|
