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 | Nanotech 2004 Vol. 2
Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 2
Chapter 3: Compact Modeling |
| | Modeling and Characterization of Wire Inductance for High Speed VLSI Design | | Authors: | N.D. Arora and L. Song | | Affilation: | Cadence Design Systems, US | | Pages: | 80 - 85 | | Keywords: | on-chip inductance, inductance modeling, inductance characterization, inductance test structures | | Abstract: | Ever increasing circuit density, operating speed, faster on-chip rise times, use of low resistance Copper (Cu) interconnects, and longer wire lengths due to high level of integration in VLSI chip designs, have necessitated the need for modeling of wire inductive (L) effects which were ignored in the past. In this paper we will review different approaches of modeling the on-chip wire inductance, and discuss practical methods of assessing the inductance with special reference to return path in an IC chip. This will be followed by discussion on impact of inductance on performance of high speed VLIS. We then cover methods of validating the models using test chip approach. | | ISBN: | 0-9728422-8-4 |
| Pages: | 519 |
| Hardcopy: | $150.00 |
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