The Development of Next Generation BSIM for Sub-100nm Mixed-Signal Circuit Simulation

	Nanotech 2004 Vol. 2 Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 2 Chapter 3: Compact Modeling
	The Development of Next Generation BSIM for Sub-100nm Mixed-Signal Circuit Simulation
Authors:	X. Xi, J. He, M. Dunga, C-H Lin, B. Heyderi, H. Wan, M. Chan, A.M. Niknejad and C. Hu
Affilation:	University of California at Berkeley, US
Pages:	70 - 73
Keywords:	MOSFETs, compact modeling, surfacepotential-plus model, small dimensional effects
Abstract:	This paper describes the next generation BSIM model for aggressively scaled CMOS technology. New features in the model include more accurate non-charge-sheet based physics, completely continuous current and derivatives, and extendibility to non-traditional CMOS based devices including SOI and double-gate MOSFETs.
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ISBN:	0-9728422-8-4
Pages:	519
Hardcopy:	$79.95

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