Nano Science and Technology Institute
Nanotech 2004 Vol. 1
Nanotech 2004 Vol. 1
Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 1
 
Chapter 11: Wafer and MEMS Processing
 

Inverse RIE Lag of Silicon Deep Etching

Authors:C.K. Chung and H.N. Chiang
Affilation:National Cheng Kung University, TW
Pages:481 - 484
Keywords:inverse, RIE Lag, deep etching, ICP, MEMS
Abstract:This paper reports for the first time that the phenomena and reaction mechanism of inverse reactive ion etching (RIE) lag occurs in the silicon deep RIE process without feature coalescence. This phenomenon is related to two important parameters of feature area and process pressure. Increasing the process pressure in different patterns with equivalent feature area will increase the etching rates as well the smaller width has higher increasing etching rate ratio. So, the smaller feature pattern has the chance to get higher etching rate than the larger one as the pressure increased is high enough. This will lead to three stages of RIE lag transition: reduced RIE lag, lag elimination and inverse RIE lag. A possible new reaction mechanism exists in the inverse RIE lag phenomena. The increasing etching rate ratio of different feature sizes is affected more obvious by CxFy radicals dissociated from C4F8 passivation gas than F radicals or SFx ions dissociated from SF6 etching gas. It will be much helpful for the process control of etching uniformity, 2D-3D simulator establishment, and the application for different level or curved surface device.
Inverse RIE Lag of Silicon Deep EtchingView PDF of paper
ISBN:0-9728422-7-6
Pages:521
Hardcopy:$79.95
 
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