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 | Nanotech 2004 Vol. 1
Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 1
Chapter 11: Wafer and MEMS Processing |
| | Process Factors in the Reduction of Output Conductance in Sub-micron CMOS | | Authors: | N.C. May, H.S. Tan and A.V. Kordesch | | Affilation: | SILTERRA (M) SDN BHD, MY | | Pages: | 477 - 480 | | Keywords: | output conductance, early voltage, DIBL, Rout, channel engineering | | Abstract: | CMOS Analog circuits require transistors with low output conductance (gds) in order to achieve high gain. Submicron MOSFETs with halo implants and retrograde wells are designed to have high transconductance (gm) but often suffer from poor output conductance. In this paper we investigated the process factors affecting gds and we show how to optimize gds. Our experimental results from 180nm CMOS are compared with 2D simulations in order to understand the mechanisms involved. Output conductance is the derivative of the ID-VD curve, gds = dID/dVD. In saturation, several effects contribute to the increase of ID with VD, namely channel length modulation (CLM), drain-induced barrier lowering (DIBL), and substrate current body effect (SCBE). We have mainly focused on PMOS transistors at voltages where the substrate current is not significant. | | ISBN: | 0-9728422-7-6 |
| Pages: | 521 |
| Hardcopy: | $150.00 |
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