Wafer and MEMS Processing

	Nanotech 2004 Vol. 1 Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 1 Chapter 11: Wafer and MEMS Processing
-	Planarize the Sidewall Ripples of Silicon Deep Reactive Ion Etching
	K-Y Weng, M-Y Wang and P-H Tsai
	Industrial Technology Research Institute, TW
-	Process Factors in the Reduction of Output Conductance in Sub-micron CMOS
	N.C. May, H.S. Tan and A.V. Kordesch
	SILTERRA (M) SDN BHD, MY
-	Inverse RIE Lag of Silicon Deep Etching
	C.K. Chung and H.N. Chiang
	National Cheng Kung University, TW
-	Microscope Slide Electrode Chamber for Nanosecond, Megavolt-Per-Meter Biological Investigations
	Y. Sun, P.T. Vernier, M. Behrend, L. Marcu and M.A. Gundersen
	University of Southern California, US
-	Numerical Analysis of Nano-imprinting Process Based on Continuum Hypothesis
	H.C. Kim, Y.S. Woo, W.I. Lee, S.I. Oh and B.S. Kim
	School of Mechanical and Aerospace Engineering, Seoul National University., KR
ISBN:	0-9728422-7-6
Pages:	521
Hardcopy:	$79.95

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