Nano Science and Technology Institute
Nanotech 2003 Vol. 3
Nanotech 2003 Vol. 3
Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 3
 
Chapter 5: Surfaces and Films
 

MEMS Fabrication Modeling with ChISELS: A Massively Parallel 3-D Level-Set Based Feature Scale Modeler

Authors:L.C. Musson, S.J. Plimpton and R.C. Schmidt
Affilation:Sandia National Laboratories, US
Pages:231 - 234
Keywords:MEMS, level-set, feature scale, ballisitc transport
Abstract:We are developing ChISELS (Chemically Induced Surface Evolution with Level-Sets), a parallel code to model 3-D material depositions and etches at feature scales on patterned wafers at low pressures. ChISELS is a platform on which to build and improve upon previous feature-scale modeling tools while taking advantage of the most recent advances in load balancing and scalable solution algorithms. The framework in which the ChISELS code is built is based upon the level-set method for modeling evolving interfaces. The level-set method, an implicit interface tracking technique, was chosen for its natural ability to handle changes in topology that frequently occur, for example, when films are grown in high aspect-ratio features in MEMS devices. The hyperbolic partial differential equation that, based on interface velocities determined from the physics of a growth or etch problem, governs the evolution of the level-set function is solved by the semi-Lagrangian method. The semi-Lagrangian method is used here because, (1) it works well for hyperbolic systems without special treatments (e.g. upwinding), (2) time integration is explicit and only interpolation on the grid is required to solve for the level-set function at the next time step, and (3) it is well-suited to the massively parallel computing environments used at Sandia National Laboratories. The meshes used in ChISELS are quad-trees (2-D) and oct-trees (3-D). The quad-trees are constructed such that the grid is refined only in the region of the interface. As the interface evolves, the static mesh is continually reconstructed so that the grid remains fine only around the interface. For parallel computation, the grid is distributed across the processors with each one owning a compact sub-domain. Each time the mesh is refined and coarsened, the load balance across processors is re-evaluated and redistributed so that the load remains evenly balanced regardless of changes in the grid.
MEMS Fabrication Modeling with ChISELS: A Massively Parallel 3-D Level-Set Based Feature Scale ModelerView PDF of paper
ISBN:0-9728422-2-5
Pages:560
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