A Unified Environment for the Modeling of Ultra Deep Submicron MOS Transistors

	Nanotech 2003 Vol. 2 Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2 Chapter 7: Compact Modeling
	A Unified Environment for the Modeling of Ultra Deep Submicron MOS Transistors
Authors:	T. Gneiting
Affilation:	Advanced Modeling Solutions, DE
Pages:	368 - 371
Keywords:	MOSFET, compact models, model parameter, extraction
Abstract:	This paper discusses the aspects of modern MOS modeling requirements. Starting fro the fact, that even the Compact Model Council (CMC) outlined BSIM3v3 as a standard MOS simulation mode, many other models are used throughout the semiconductor community. Their common approach is they are all highly scalable to cover a wide range of transistor dimensions. To cover this effect, a strategy for efficient model parameter extraction with a special emphasis on scalability is illustrated. This leads to a software architecture and a data base concept, which enables modeling engineers to handle the parameter extraction for different simulation models from one common measurement base in a very efficient and flexible way.
	View PDF of paper
ISBN:	0-9728422-1-7
Pages:	600
Special:	3 CD Set — 15% off with Free Shipping
Up