Unified RLC Model for On-Chip Interconnects

	Nanotech 2003 Vol. 2 Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2 Chapter 7: Compact Modeling
	Unified RLC Model for On-Chip Interconnects
Authors:	S-P. Sim and C. Yang
Affilation:	Santa Clara University, US
Pages:	356 - 359
Keywords:	on-chip interconnects, compact modeling, capacitance, inductance
Abstract:	We present a unified RLC model for deep sub-micron on-chip interconnects. The model consists of two components, a quasi-3D capacitance extraction based on a novel concept of 'effective width' and a effective loop inductance model. In the quasi-3D capacitance model, the effective width provides and efficient way to decompose any 3D structure into a series of 2D segments, resulting in an accurate capacitance extraction. Validation and extraction methodology for the effective loop inductance, which is more computationally efficient than the partial inductance approach, will be addressed. Random capacitive coupling effect, which is important at high frequencies, will be investigated through a full-wave solver and S-parameter analysis, leading to a frequency-dependent RLC model valid up to 100 GHz.
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ISBN:	0-9728422-1-7
Pages:	600
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