Authors: M-H Chiang, J.X. An, Z. Krivokapic and B. Yu
Affilation: AMD, United States
Pages: 326 - 329
Keywords: FinFET, double-gate
Interest in the double-gate (DG) MOSFET has been growing as transistor development is approaching the end of SIA roadmap. Recent progress in DG technology, and some theoretical study have promoted DG to one of the emerging non-classical CMOS candidates. In order to fully explore the uniqueness and benefit of DG it is indispensable to assess DG CMOS circuit performance, especially with parasitic included. In this work, DG look-up-table models are generated for the first time for symmetric and asymmetric gates at ITRS 45nm technology node. The models are used to compare DG with single gate in inverter and NAND ring oscillators with and without interconnect capacitive loading. Parasitic gate resistance effect in DG-CMOS performance is also evaluated. A developing UF-DG compact model is further used for more device scaling analyses.