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 | Nanotech 2003 Vol. 2
Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2
Chapter 7: Compact Modeling |
| | Gate Current Partitioning in MOSFET Models for Circuit Simulation | | Authors: | Q. Ngo, D. Navarro, T. Mizoguchi, S. Hosakawa, H. Ueno, M. Miura-Mattausch and C.Y. Yang | | Affilation: | Santa Clara University, US | | Pages: | 322 - 325 | | Keywords: | gate current, paritioning, compact modeling, surface-potential-based model | | Abstract: | Gate current plays a critical role in circuits featuring sub-100nm MOSFETs. This paper elucidates the importance of gate current partitioning for accurate circuit simulation. Past publications have presented gate current models based on surface potential [1]. However the calculation of surface potential was based largely on long-channel assumptions. As the trend of developing surface-potential-based circuit simulation models continues to grow, we demonstrate that using one such model, HiSIM (Hiroshima STARC IGFET Model), to simulate gate current provides reasonably accurate results when compared to measurement data. A gate current partition model is presented based on the HiSIM formulation of inversion charge partitioning. [1] C-H. Choi, K-H Oh, J-S Goo, Z. Yu, and R.W. Dutton, Direct Tunneling Current Model for Circuit Simulation, IEDM Tech. Dig. 1999, pp. 735 |  | View paper | | ISBN: | 0-9728422-1-7 |
| Pages: | 600 |
| Hardcopy: | $125.00 |
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