Nano Science and Technology Institute
Nanotech 2003 Vol. 2
Nanotech 2003 Vol. 2
Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2
Chapter 4: Nano Electronics

Logic Optimization and Technology Mapping for CAEN

Authors:P. Färm, E. Dubrova and H. Tenhunen
Affilation:IMIT, KTH, SE
Pages:145 - 148
Keywords:caen, chemically assembled nanotechnology, logic optimization, technology mapping
Abstract:This paper considers the architectures and design issues involved in creating a nano-electronic computing system. We focus on the problems of technology dependent optimization and technology mapping for Chemically Assembled Electronic Nanotechnology (CAEN). We present an experimental tool which optimizes an input circuit description and maps it into a two-dimensional homogeneous array of interconnected molecular logic blocks. The experimental results show that the CPU time of the tool is less than half a second even for quite large benchmarks.
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