Simulation of Mixed-Signal Systems in Standard VHDL

	MSM 98 Technical Proceedings of the 1998 International Conference on Modeling and Simulation of Microsystems Chapter 6: Equivalent Circuits, Behavioral and Multilevel Simulation
	Simulation of Mixed-Signal Systems in Standard VHDL
Authors:	H. Grätz and W-J Fischer
Affilation:	Fraunhofer-Institute of Microelectronic Circuits and Systems, DE
Pages:	228 - 232
Keywords:	mixed signal simulation, VHDL, system simulation
Abstract:	Historically, the analogue and digital parts of a hardware design have been modelled and simulated in different environments and could not be combined in a single simulator. On the other hand, if a design contains both analog and digital parts simulating their interactions are most important to reiiably verify the design. Therefore, we present a method for simulating analogue circuits and digital components in a VHDL simulator. For executing analogue simulations in a VHDL environment an analogue simulator has been developed. It permits to model linear and non-linear circuits using only standard VHDL language elements. This fact allows a similar conversion of this method to different VHDL environments. A netlist is used to model the analogue parts with elements from a model library. In order to interface analogue and digital parts A/D and D/A converter elements are be used. This allows signal feedbacks between both parts during the simulation.
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ISBN:	0-96661-35-0-3
Pages:	678
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